1. Field of the Invention
The present invention relates to an electronic device test apparatus for testing semiconductor integrated circuit devices and various other electronic devices (hereinafter also referred to representatively as “IC chips”), more particularly relates to an electronic device test apparatus enabling a large number of types of electronic devices under test (“DUTs”) to be easily handled.
2. Description of the Related Art
In an IC test apparatus (electronic device test apparatus) called a “handler”, a large number of IC chips stored on a tray are conveyed inside the handler, the IC chips are brought into electrical contact with a test head, and the electronic device test apparatus unit (hereinafter, also referred to as a “tester”) is made to conduct the tests. Further, after the tests are completed, the IC chips are ejected from the test head and transferred onto a tray in accordance with the test results to thereby separate the chips into good ones and defective ones.
In general, in an electronic device test apparatus for testing memory IC chips, which require a relatively long test time (hereinafter, also referred to as “memory ICs”) (hereinafter, also referred to as a “memory IC test apparatus”), a larger number of IC chips are transferred before and after the tests between trays storing before-test/after-test IC chips (hereinafter, also referred to as “customer trays”) and trays conveyed circulated within the electronic device test apparatus (hereinafter, also referred to as “test trays”). The IC chips are passed through chambers of high temperature or low temperature environments where they are subjected to high temperatures or low temperatures of −55 to 150° C. or so and are simultaneously pushed against the test head for testing in the state placed on the test trays.
As a test tray used in such a memory IC test apparatus, one is known which is provided with a plurality of inserts for holding the IC chips and inserts guide pins provided at contact units of the test head into guide holes formed at the inserts when pushing the IC chips against the test head so as to accurately position the input/output terminals of the IC chips and the contact pins of the contact units to thereby prevent poor contact at the time of tests (for example, see Japanese Patent Publication (A) No. 2001-33519).
However, the inserts provided at such a test tray are designed to constrain the movement of the IC chips based on the outside shapes of the IC chips, that is, are dedicated units designed for the outside shapes of specific types of IC chips. It is therefore necessary to prepare in advance test trays provided with inserts corresponding to the specific types of IC chips and necessary to exchange the test trays with ones designed to handle the types of the IC chips being tested each time the types of the IC chips under test change. Therefore, in a memory IC test apparatus using such test trays, the exchange time when changing types of IC chips cannot be shortened. In particular, it is not possible to increase the efficiency of tests when testing small amounts of a variety of types of devices.
As opposed to this, as a memory IC test apparatus able to easily handle a large variety of types of IC chips, one which employs a test plate having substantially smooth holding surfaces in place of such test trays and uses these smooth holding surfaces to hold the back surfaces of the IC chips where input/output terminals are not led out may be considered. Due to this, it would be possible to hold IC chips without regard as to the outside shapes of the IC chips, so there would no longer be a need to prepare test trays for specific types of IC chips and exchange of trays at the time of changing types of IC chips tested would become unnecessary. This could therefore be an effective means for realizing a memory IC test apparatus able to easily handle a large variety of types of IC chips.
On the other hand, as an electronic device test apparatus for logic IC chips, where the test times are shorter than with memory ICs (hereinafter, also referred to as a “logic IC test apparatus”), one is known which does not use the above test trays, but uses a CCD camera and an image processing system etc. to compute the relative position of an IC chip with respect to a contact unit and positions that IC chip relative to it by a moving means with a high precision based on the results of computation. This enables poor contact at the time of testing to be prevented without regard as to the outside shapes of the IC chips (for example, see WO03/075023 pamphlet).
The method of using this image processing enables high precision positioning of the IC chips allowing even variation in the relative positions of the input/output terminals with respect to the outside shapes of the IC chips arising in the production process, it it may be considered effective to apply this to a memory IC test apparatus using the above test plate so as to prevent poor contact. However, in having holding surfaces of the test plate hold the back surfaces of IC chips where input/output terminals are not led out, the moving means has to pick up the front surfaces of the IC chips where the input/output terminals are led out, so the moving means becomes an obstacle when the CCD camera captures images of them, it is difficult to accurately capture image of the input/output terminals of the IC chips, high precision positioning of the IC chips is not possible, and poor contact cannot be sufficiently prevented. This is particularly true in ultra small IC chips such as the recent flash memories.